As for network supported products capable of performing communication by being connected to a communication network, it has been controlled in each region to limit a power consumption value when an operation state of the product is in a standby state. The standby state means a state in which it is possible to resume a function of a product by, for example, a trigger from outside via a network.
To reduce the power consumption in the standby state, there is a system in which a CPU (Central Processing Unit) and a RAM (Random Access Memory) as a normal system are held, and a CPU and a RAM each of whose power consumption at the operation time is lower than the normal system are held as a standby system. When an amount of processes at the system is small, the normal system consuming a large power is stopped, the processes are executed by switching to the standby system whose power consumption is low to thereby reduce the power consumption of the system as a whole in time series.
FIG. 14A is a view illustrating an example of an information processing system including a main CPU and a sub CPU. The information processing system illustrated in FIG. 14A includes a main CPU 418 and a RAM 419 as the normal system mainly performing processes at a normal operation state, and a sub CPU 420 and a RAM 421 as the standby system performing the processes at a standby state, and is connected to a network via a network interface part 411.
The network interface part 411 includes a direct memory access (DMA) controller 412, a media access control (MAC) part 413, and a physical (PHY) part 414. The DMA controller 412 is a DMA controller in a descriptor type executing instructions cited at the RAM, and a reception DMA processing part 416 performs processes relating to reception and a transmission DMA processing part 417 performs processes relating to transmission based on a descriptor stored at the RAM 419 or the RAM 421.
FIG. 14B is a view illustrating an internal configuration of the DMA controller. A DMA controller 430 includes a reception DMA channel 431, a transmission DMA channel 441, a descriptor read/write processing part 451, a data read/write processing part 452, and a packet data saving buffer 453. The descriptor read/write processing part 451 performs processes relating to read and write of descriptor information, the data read/write processing part 452 performs processes relating to data transmitted and received via a MAC part 454. The packet data saving buffer 453 is a buffer holding received packet data.
The reception channel 431 includes a base address register 432, a current address register 433, an end address register 434, a register of the number of remaining packets 435, a restart processing part 436, and a control part 437. A first address of a descriptor 456 put on a RAM 455 is stored at the base address register 432. An end address of the descriptor 456 put on the RAM 455 is stored at the end address register 434. An address of a descriptor corresponding to a packet which is processed next is stored at the current address register 433. Address information of the RAM where the packets are actually disposed, length information of the packet, and information for the process of the packet are included in the descriptor 456.
The register of the number of remaining packets 435 has a function indicating the number of unprocessed packets (remaining packets) at the DMA channel. The restart processing part 436 has a function receiving instructions to stop and start the DMA channel from the main CPU and the sub CPU. When the instruction to stop the DMA channel is received from either of the CPUs, the restart processing part 436 stops a transfer process of a packet data belonging to the DMA channel, and performs a process to clear descriptor information of the DMA channel. Besides, when the instruction to start the DMA channel is received from either of the CPUs, the restart processing part 436 registers a value of the base address register 432 to the current address register 433, performs a process to clear the register of the number of remaining packets 435, and starts a DMA operation. The control part 437 controls information stored at each of the registers 432 to 435.
The transmission channel 441 includes a base address register 442, a current address register 443, an end address register 444, a register of the number of remaining packets 445, a restart processing part 446, and a control part 447. Note that each of functions of these and so on are similar to those of the base address register 432, the current address register 433, the end address register 434, the register of the number of remaining packets 435, the restart processing part 436, and the control part 437 held by the reception channel 431.
An operation flow of the DMA controller 430 is described while using a packet reception as an example. The DMA controller 430 registers the first address of the descriptor 456 to the base address register 432 in an initialization. The DMA controller 430 acquires descriptor information while setting the address registered to the base address register 432 as a first current storage position of the descriptor 456. The DMA controller 430 opens the packet data received in the RAM 455 based on the acquired information, and reflects length information and a process state on the descriptor when one packet is reception-processed. Next, the DMA controller 430 increments a value of the address held by the current address register 433, and acquires next descriptor information. The DMA controller 430 opens the received packet data in the RAM 455 based on the acquired descriptor information when a next packet is received. Subsequently, the process is repeated similarly for the number of received packets.
In the information processing system illustrated in FIG. 14A, when a mode is switched from a normal operation state (normal mode) in which the process is performed by using the main CPU 418 and the RAM 419 being the normal system to a standby state (standby mode) in which the process is performed by using the sub CPU 420 and the RAM 421 being the standby system, and when the mode is switched from the standby mode to the normal mode, new address information relating to the descriptor relative to the DMA controller 430 is set again. FIG. 15 is a flowchart illustrating an operation example including the mode switching of the information processing system illustrated in FIG. 14A. Note that the sub CPU 420 is constantly activated at both the normal mode time and the standby mode time to perform a management of the mode switching. The main CPU 418 is activated at the normal mode time, and stops at the standby mode time.
When the operation is started, the sub CPU 420 is activated (S801). When it is the process using the main CPU 418, namely, when it is the normal mode (TRUE in S802), the main CPU 418 is activated (S803). On the other hand, when it is not the process using the main CPU 418, namely, when it is the standby mode (FALSE in S802), electricity to the main CPU 418 and the RAM 419 is turned off (S804). Subsequently, the DMA controller 430 is reset (S805). After that, the DMA controller 430 is initialized, and after the first address of the descriptor on the RAM is registered to the base address registers 432, 442 (S806), the DMA controller 430 is activated (S807).
After that, the packet transfer process using the DMA controller 430 is performed (S808). At this time, when an instruction of the mode switching from the normal mode to the standby mode, or from the standby mode to the normal mode is received (TRUE in S809), the DMA operation by the DMA controller 430 is stopped (S810), and the process returns to the step S802. Then, the above-stated processes are performed again in accordance with the mode to be switched.
A DMA transfer unit having plural channels provided to correspond to plural input/output units, and exchanging each of them in accordance with a channel priority order, to perform a DMA transfer is proposed (for example, Patent Document 1). A DMA control method selecting one DMA channel from among plural DMA channels in accordance with a register drawing out a priority level which corresponds to a DMA request signal from each I/O is proposed (for example, Patent Document 2). A technology in which usage of a DMA channel is continued until a data transfer using the DMA channel which is in use reaches a boundary condition set in advance, and when the boundary condition occurs, the DMA channel moves to a next DMA channel is proposed (for example, Patent Document 3). A technology in which a sub CPU moves data stored at an SRAM to a DRAM when a state returns to a state performing a process by a main CPU from a state performing a process by the sub CPU is proposed (for example, Patent Document 4).
[Patent Document 1] Japanese Laid-open Patent Publication No. 02-96261
[Patent Document 2] Japanese Laid-open Patent Publication No. 62-50946
[Patent Document 3] Japanese Laid-open Patent Publication No. 10-40211
[Patent Document 4] Japanese Laid-open Patent Publication No. 2010-74256
In the information processing system illustrated in FIG. 14A, processes such as the stop (S810), the reset (S805), and the initialization (S806) of the DMA controller occur as illustrated in FIG. 15 at a transition from the normal mode to the standby mode, and a transition from the standby mode to the normal mode. Accordingly, when a new packet is received from a network during these processes, in other words, during a period when the step S810 and the subsequent steps S802 to S806 illustrated in FIG. 15 are performed, there is a problem in which the packet is dropped out to incur a packet loss.